Display panel

ABSTRACT

A display panel includes: a first substrate having a top surface and a side surface, the top surface including a display area and a non-display area outside the display area; a second substrate facing the first substrate; a first insulating structure disposed between the second substrate and the first substrate, wherein the first insulating structure overlaps the non-display area without overlapping the display area; an organic light emitting diode between the first substrate and the second substrate and overlapping the display area; a thin film encapsulation layer on the organic light emitting diode; a signal line having a side surface substantially aligned with the side surface of the first substrate, wherein the signal line is disposed on the first substrate; a second insulating structure overlapping the signal line and disposed between the first substrate and the first insulating structure, wherein the second insulating structure has a side surface substantially aligned with the side surface of the first substrate; and a connection pad being in contact with the side surface of the signal line, wherein the second insulating structure includes an organic layer overlapping the signal line and the non-display area without overlapping the display area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application is a Continuation of U.S.patent application Ser. No. 16/922,998, filed on Jul. 7, 2020, which isa Continuation of U.S. patent application Ser. No. 16/139,390, filedSep. 24, 2018, which claims priority to and the benefit of Korean PatentApplication No. 10-2017-0123750, filed on Sep. 25, 2017, which is herebyincorporated by reference for all purposes as if fully set forth herein.

BACKGROUND Field

Embodiments of the invention relate generally to a display panel and,more specifically, to a display panel having a sturdy structure andlarge viewing area.

Discussion of the Background

Generally, after a display panel is manufactured, a printed circuitboard (PCB) is connected to the display panel. For example, in a tapeautomated bonding (TAB) mounting method, the PCB is bonded to thedisplay panel using an anisotropic conductive film (ACF). Typically, thePCB has a planar shape that extends from the display panel in adirection generally parallel to the display panel after connection,which increases the overall dimensions of the display panel.

Recently, display panel design techniques for reducing a bezel area (ora non-display area) have been variously studied.

The above information disclosed in this Background section is only forunderstanding of the background of the inventive concepts, and,therefore, it may contain information that does not constitute priorart.

SUMMARY

Display panels constructed according to embodiments of the inventionhave a PCB that connects to a side surface of a display panel, which mayimprove structural integrity and provide a more compact configurationthat reduces the non-display area and/or improve the electricalconnection between the PCB and a signal line, and may prevent the signalline from being damaged and/or deformed in a manufacturing process suchas a grinding process.

Additional features of the inventive concepts will be set forth in thedescription which follows, and in part will be apparent from thedescription, or may be learned by practice of the inventive concepts.

According to one or more embodiments of the invention, a display panelincludes a first substrate having a top surface and a side surfaceextending in a direction intersecting the top surface, a secondsubstrate facing the first substrate, an insulating layer disposedbetween the first substrate and the second substrate, a first insulatingstructure disposed between the insulating layer and the first substrate,a pixel disposed between the first substrate and the second substrate, asignal line having a side surface substantially aligned with the sidesurface of the first substrate, a second insulating structureoverlapping the signal line and being in contact with the firstinsulating structure, and a connection pad being in contact with theside surface of the first substrate, the side surface of the signalline, and the side surface of the second insulating structure. The firstinsulating structure is in contact with the insulating layer, the signalline is disposed on the first substrate, and the second insulatingstructure has a side surface substantially aligned with the side surfaceof the first substrate.

The second insulating structure may include an organic layer overlappingthe signal line, and an inorganic layer disposed on the organic layer.

The pixel may include a first electrode, a second electrode insulatedfrom the first electrode, a thin film transistor electrically connectedto the first electrode, and a liquid crystal layer controlled by anelectric field formed between the first electrode and the secondelectrode.

The display panel may further include a spacer overlapping the thin filmtransistor. The first electrode and the second electrode may overlapeach other and may be spaced apart from each other in a thicknessdirection of the first substrate, the inorganic layer may extend tooverlap the thin film transistor, the second electrode may overlap thethin film transistor, and the spacer may be disposed between a portionof the inorganic layer overlapping the thin film transistor and aportion of the second electrode overlapping the thin film transistor.

The first insulating structure and the spacer may include substantiallythe same material.

The display panel may further include a color filter disposed betweenthe first substrate and the first electrode and overlapping the firstelectrode.

The inorganic layer may extend to overlap the color filter and is incontact with the color filter.

The organic layer and the color filter may include substantially thesame material.

The signal line may be disposed on substantially the same layer as acontrol electrode of the thin film transistor.

The display panel may further include a seal spaced apart from theorganic layer of the second insulating structure. The seal may surroundthe liquid crystal layer.

The display may further include a floating electrode overlapping thesignal line and the second insulating structure. The floating electrodemay be disposed between the signal line and the organic layer of thesecond insulating structure.

The floating electrode may be disposed on substantially the same layeras an input electrode or an output electrode of the thin filmtransistor.

The display panel may further include a circuit substrate electricallyconnected to the connection pad.

The pixel may include a first electrode, a second electrode insulatedfrom the first electrode, a thin film transistor electrically connectedto the first electrode, and a light emitting layer disposed between thefirst electrode and the second electrode.

The signal line may include copper, and the connection pad may includesilver paste.

According to one or more embodiments of the invention, a display panelincludes a first substrate having a top surface and a side surfaceextending in a direction intersecting the top surface, a secondsubstrate facing the first substrate, electrodes disposed between thefirst substrate and the second substrate, a liquid crystal layerdisposed between the first substrate and the second substrate, a sealingstructure disposed between the first substrate and the second substrateand configured to surround the liquid crystal layer, an insulatingstructure disposed between the first substrate and the second substrateand disposed outside of the sealing structure, a signal line having aside surface substantially aligned with the side surface of the firstsubstrate, and a connection pad being in contact with the side surfaceof the first substrate, the side surface of the signal line, and theside surface of the insulating structure. The insulating structure has aside surface substantially aligned with the side surface of the firstsubstrate and includes layers different from that of the sealingstructure. The signal line is disposed on the first substrate andoverlaps the insulating structure,

The insulating structure may surround the sealing structure.

The sealing structure may have a single-layered structure, and theinsulating structure may include at least two stacked, organic layers.

The insulating structure may further include an inorganic layer disposedbetween the two organic layers.

The electrodes may include a first electrode and a second electrodespaced apart from each other, the liquid crystal layer may be disposedbetween the first electrode and the second electrode, the sealingstructure may be in contact with one of the first electrode and thesecond electrode, and the insulating structure may be spaced apart fromthe first electrode and the second electrode.

According to one or more embodiments of the invention, a display panelincludes: a first substrate having a top surface and a side surface, thetop surface including a display area and a non-display area outside thedisplay area; a second substrate facing the first substrate; a firstinsulating structure disposed between the second substrate and the firstsubstrate, wherein the first insulating structure overlaps thenon-display area without overlapping the display area; an organic lightemitting diode between the first substrate and the second substrate andoverlapping the display area; a thin film encapsulation layer on theorganic light emitting diode; a signal line having a side surfacesubstantially aligned with the side surface of the first substrate,wherein the signal line is disposed on the first substrate; a secondinsulating structure overlapping the signal line and disposed betweenthe first substrate and the first insulating structure, wherein thesecond insulating structure has a side surface substantially alignedwith the side surface of the first substrate; and a connection pad beingin contact with the side surface of the signal line, wherein the secondinsulating structure includes an organic layer overlapping the signalline and the non-display area without overlapping the display area.

The first insulating structure and the second insulating structure maybe disposed on the thin film encapsulation layer.

The second substrate may be spaced apart from the thin filmencapsulation layer.

The display panel may further include a pixel defining layer on thefirst substrate, and wherein the first insulating structure and thesecond insulating structure are disposed on pixel defining layer.

The display panel may further include a thin film transistorelectrically connected to the organic light emitting diode, and whereinthe signal line is disposed on substantially the same layer as a controlelectrode of the thin film transistor.

The display panel may further include a seal disposed between the firstsubstrate and the second substrate and spaced apart from the organiclayer of the second insulating structure.

The display panel may further include a floating electrode overlappingthe signal line and the second insulating structure, wherein thefloating electrode is disposed between the signal line and the organiclayer of the second insulating structure.

The floating electrode may contact the connection pad.

The display panel may further include a thin film transistorelectrically connected to the organic light emitting diode, and whereinthe floating electrode is disposed on substantially the same layer as aninput electrode or an output electrode of the thin film transistor.

The display panel may further include a circuit substrate electricallyconnected to the connection pad.

The signal line may include copper, and the connection pad may includesilver paste.

The second insulating structure may contact the first insulatingstructure.

The connection pad may contact the side surface of the first substrateand the side surface of the second insulating structure.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention, andtogether with the description serve to explain the inventive concepts.

FIG. 1 is a schematic perspective view of an embodiment of a displaydevice constructed according to the principles of the invention.

FIG. 2 is a schematic plan view of the display device of FIG. 1.

FIG. 3 is a schematic, partial perspective view of a display area of adisplay panel of the display device of FIG. 1.

FIG. 4 is a schematic, partial perspective view of a non-display area ofa display panel of the display device of FIG. 1.

FIG. 5 is an equivalent circuit diagram of a pixel of a display panel ofthe display device of FIG. 2.

FIGS. 6A to 6C are schematic cross-sectional views of display areas ofdisplay panels constructed according to some embodiments of theinvention.

FIG. 7 is a schematic cross-sectional view of a non-display area of adisplay panel constructed according to an embodiment of the invention.

FIG. 8 is a cross-sectional image of a non-display area of a displaypanel constructed according to an embodiment of the invention.

FIG. 9A is a schematic perspective view of a work panel used in anexemplary method of manufacturing a display panel according to anembodiment of the invention.

FIG. 9B is a schematic cross-sectional view of the work panel of FIG.9A.

FIG. 9C is a schematic cross-sectional view of a preliminary displaypanel cut from the work panel of FIG. 9A.

FIG. 9D is a cross-sectional image of a display panel as a comparativeexample.

FIG. 10 is a schematic cross-sectional view of a non-display area of adisplay panel constructed according to an embodiment of the invention.

FIG. 11 is an equivalent circuit diagram of a pixel that may be employedin any of the display panels constructed according to an embodiment ofthe invention.

FIG. 12 is a schematic cross-sectional view of a display area of adisplay panel constructed according to an embodiment of the invention.

FIG. 13 is a schematic cross-sectional view of a non-display area of adisplay panel constructed according to an embodiment of the invention.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of various embodiments or implementations ofimplementations of the invention. As used herein “embodiments” and“implementations” are interchangeable words that are non-limitingexamples of devices or methods employing one or more of the inventiveconcepts disclosed herein. It is apparent, however, that variousembodiments may be practiced without these specific details or with oneor more equivalent arrangements. In other instances, well-knownstructures and devices are shown in block diagram form in order to avoidunnecessarily obscuring various embodiments. Further, variousembodiments may be different, but do not have to be exclusive. Forexample, specific shapes, configurations, and characteristics of anembodiment may be used or implemented in another embodiment withoutdeparting from the inventive concepts.

Unless otherwise specified, the illustrated embodiments are to beunderstood as providing exemplary features of varying detail of someways in which the inventive concepts may be implemented in practice.Therefore, unless otherwise specified, the features, components,modules, layers, films, panels, regions, and/or aspects, etc.(hereinafter individually or collectively referred to as “elements”), ofthe various embodiments may be otherwise combined, separated,interchanged, and/or rearranged without departing from the inventiveconcepts.

The use of cross-hatching and/or shading in the accompanying drawings isgenerally provided to clarify boundaries between adjacent elements. Assuch, neither the presence nor the absence of cross-hatching or shadingconveys or indicates any preference or requirement for particularmaterials, material properties, dimensions, proportions, commonalitiesbetween illustrated elements, and/or any other characteristic,attribute, property, etc., of the elements, unless specified. Further,in the accompanying drawings, the size and relative sizes of elementsmay be exaggerated for clarity and/or descriptive purposes. When anembodiment may be implemented differently, a specific process order maybe performed differently from the described order. For example, twoconsecutively described processes may be performed substantially at thesame time or performed in an order opposite to the described order.Also, like reference numerals denote like elements.

When an element, such as a layer, is referred to as being “on,”“connected to,” or “coupled to” another element or layer, it may bedirectly on, connected to, or coupled to the other element or layer orintervening elements or layers may be present. When, however, an elementor layer is referred to as being “directly on,” “directly connected to,”or “directly coupled to” another element or layer, there are nointervening elements or layers present. To this end, the term“connected” may refer to physical, electrical, and/or fluid connection,with or without intervening elements. Further, the D1-axis, the D2-axis,and the D3-axis are not limited to three axes of a rectangularcoordinate system, such as the x, y, and z-axes, and may be interpretedin a broader sense. For example, the D1-axis, the D2-axis, and theD3-axis may be perpendicular to one another, or may represent differentdirections that are not perpendicular to one another. For the purposesof this disclosure, “at least one of X, Y, and Z” and “at least oneselected from the group consisting of X, Y, and Z” may be construed as Xonly, Y only, Z only, or any combination of two or more of X, Y, and Z,such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

Although the terms “first,” “second,” etc. may be used herein todescribe various types of elements, these elements should not be limitedby these terms. These terms are used to distinguish one element fromanother element. Thus, a first element discussed below could be termed asecond element without departing from the teachings of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “under,” “lower,”“above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), andthe like, may be used herein for descriptive purposes, and, thereby, todescribe one elements relationship to another element(s) as illustratedin the drawings. Spatially relative terms are intended to encompassdifferent orientations of an apparatus in use, operation, and/ormanufacture in addition to the orientation depicted in the drawings. Forexample, if the apparatus in the drawings is turned over, elementsdescribed as “below” or “beneath” other elements or features would thenbe oriented “above” the other elements or features. Thus, the exemplaryterm “below” can encompass both an orientation of above and below.Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90degrees or at other orientations), and, as such, the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments and is not intended to be limiting. As used herein, thesingular forms, “a,” “an,” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. Moreover,the terms “comprises,” “comprising,” “includes,” and/or “including,”when used in this specification, specify the presence of statedfeatures, integers, steps, operations, elements, components, and/orgroups thereof, but do not preclude the presence or addition of one ormore other features, integers, steps, operations, elements, components,and/or groups thereof. It is also noted that, as used herein, the terms“substantially,” “about,” and other similar terms, are used as terms ofapproximation and not as terms of degree, and, as such, are utilized toaccount for inherent deviations in measured, calculated, and/or providedvalues that would be recognized by one of ordinary skill in the art.

Various embodiments are described herein with reference to sectionaland/or exploded illustrations that are schematic illustrations ofidealized embodiments and/or intermediate structures. As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments disclosed herein should not necessarily beconstrued as limited to the particular illustrated shapes of regions,but are to include deviations in shapes that result from, for instance,manufacturing. In this manner, regions illustrated in the drawings maybe schematic in nature and the shapes of these regions may not reflectactual shapes of regions of a device and, as such, are not necessarilyintended to be limiting.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure is a part. Terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the relevant art and should not be interpreted in anidealized or overly formal sense, unless expressly so defined herein.

FIG. 1 is a schematic perspective view of an embodiment of a displaydevice constructed according to the principles of the invention. FIG. 2is a schematic plan view of the display device of FIG. 1. FIG. 3 is aschematic, partial perspective view of a display area of a display panelof the display device of FIG. 1. FIG. 4 is a schematic, partialperspective view of a non-display area of a display panel of the displaydevice of FIG. 1.

Referring to FIGS. 1 and 2, display device DD includes display panel DP,gate driving unit GDC, data driving unit DDC, main circuit substrate PB,and signal controller SC. Display device DD may further include achassis member or a molding member and may further include a backlightunit depending on the type of display panel DP employed.

Display panel DP may be formed as a liquid crystal display panel, aplasma display panel, an electrophoretic display panel, amicroelectromechanical system (MEMS) display panel, an electrowettingdisplay panel, or other types of display panels known in the art.

Display panel DP may include first display substrate 100 and seconddisplay substrate 200 disposed on first display substrate 100. Eventhough not visible in FIG. 1, a gap may be formed between first displaysubstrate 100 and second display substrate 200.

As illustrated in FIG. 1, display panel DP may display an image throughdisplay surface DP-IS. Display surface DP-IS is parallel to a planedefined by first directional axis DR1 and second directional axis DR2.Display surface DP-IS may include display area DA and non-display areaNDA. Non-display area NDA may be defined along a border of displaysurface DP-IS and may surround display area DA.

A normal direction of display surface DP-IS (i.e., a thickness directionof display panel DP) is indicated by third directional axis DR3.Hereinafter, a front surface (or a top surface) and a back surface (or abottom surface) of each of layers or units may have a thickness definedin a third directional axis DR3. However, first, second and thirddirectional axes DR1, DR2 and DR3 shown in the illustrated embodimentare examples of the invention, and first, second and third directionalaxes DR1, DR2 and DR3 may be relative concepts and may be changed toother directions. Hereinafter, the first, second and third directionsare the directions indicated by first, second, and third directionalaxes DR1, DR2 and DR3, respectively, and are indicated by the samereference designators as first, second and third directional axes DR1,DR2, and DR3.

Display panel DP having a planar display surface is shown in theillustrated embodiment. However, the inventive concepts are not limitedthereto. In certain embodiments, display panel DP may include a curveddisplay surface or a three-dimensional (3D) display surface. A 3Ddisplay surface may include a plurality of display areas indicated bydifferent directions.

Gate driving unit GDC and data driving unit DDC may include circuitsubstrates GCB and DCB, which may be formed as printed circuit boards(PCBs) and driving chips GC and DC, respectively. Each of circuitsubstrates GCB and DCB has a structure in which an insulating layer anda conductive layer are stacked. The conductive layer may include aplurality of signal lines. Gate driving unit GDC and data driving unitDDC may be coupled to a side surface of display panel DP so as to beelectrically connected to signal lines of display panel DP and haveplanar shapes defined by second and third directions DR2 and DR3 thatextend generally perpendicular to the plane of the display panel definedby first and second directions DR1 and DR2. Since gate driving unit GDCand data driving unit DDC are coupled to the side surface of displaypanel DP in this manner, non-display area NDA may be reduced, comparedto the typical configuration in the planar shapes defined by the circuitsubstrates extended generally parallel to the plane of display surfaceDP-IS.

In the illustrated embodiment, gate driving unit GDC and data drivingunit DDC are coupled to different side surfaces of display panel DP.However, the inventive concepts are not limited thereto. In anotherembodiment, one of gate driving unit GDC and data driving unit DDC maybe omitted. In other embodiments, gate driving unit GDC and data drivingunit DDC may be coupled to substantially the same side surface ofdisplay panel DP, or gate driving unit GDC may be integrated on displaypanel DP through an oxide silicon gate driver circuit (OSG) process oran amorphous silicon gate driver circuit (ASG) process.

Main circuit substrate PB may be connected to circuit substrate DCB ofdata driving unit DDC. Main circuit substrate PB may be electricallyconnected to circuit substrate DCB of data driving unit DDC through ananisotropic conductive film (ACF) or solder balls. Signal controller SCmay be mounted on main circuit substrate PB. Signal controller SCreceives image data and control signals from an external graphiccontroller. Signal controller SC may provide control signals to gatedriving unit GDC and data driving unit DDC.

In an embodiment of the invention, display device DD may further includea main circuit substrate connected to circuit substrate GCB of gatedriving unit GDC. In an embodiment of the invention, driving chip DC ofdata driving unit DDC may be mounted on main circuit substrate PB.

FIG. 2 illustrates planar arrangement of signal lines GL1 to GLn, DL1 toDLm, PL-G and PL-D and pixels PX11 to PXnm in display panel DP. Signallines GL1 to GLn, DL1 to DLm, PL-G and PL-D may include a plurality ofgate lines GL1 to GLn, a plurality of data lines DL1 to DLm, andauxiliary signal lines PL-G and PL-D.

Gate lines GL1 to GLn extend in first direction DR1 and are arranged insecond direction DR2, and data lines DL1 to DLm are insulated from gatelines GL1 to GLn and intersect gate lines GL1 to GLn.

Gate lines GL1 to GLn and data lines DL1 to DLm overlap each other andare disposed in display area DA. Auxiliary signal lines PL-G and PL-Dare disposed in non-display area NDA and connected to gate lines GL1 toGLn and data lines DL1 to DLm.

First auxiliary signal lines PL-G connected to gate lines GL1 to GLn maybe disposed on substantially the same layer as gate lines GL1 to GLn andmay constitute a single unitary body with gate lines GL1 to GLn. Secondauxiliary signal lines PL-D connected to data lines DL1 to DLm may bedisposed on a layer different from the layer on which data lines DL1 toDLm are disposed. Each of data lines DL1 to DLm may be electricallyconnected to a corresponding one of second auxiliary signal lines PL-Dthrough contact hole CH penetrating at least one insulating layerdisposed between second auxiliary signal lines PL-D and data lines DL1to DLm.

In an embodiment of the invention, contact hole CH may be omitted, anddata lines DL1 to DLm and second auxiliary signal lines PL-D may bedisposed on substantially the same layer. In the illustrated embodiment,gate lines GL1 to GLn and first auxiliary signal lines PL-G aredistinguished from each other. However, in another embodiment, a gateline and a first auxiliary signal line connected to each other may bedefined as one signal line. In this case, the gate line and the firstauxiliary signal line connected to each other may be defined asdifferent portions of one signal line.

Signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D may further includeother signal lines, such as signal lines for electrically connectinggate driving units GDC to one another and signal lines for electricallyconnecting gate driving units GDC to main circuit substrate PB.

Each of pixels PX11 to PXnm is connected to a corresponding one of gatelines GL1 to GLn and a corresponding one of data lines DL1 to DLm. Eachof pixels PX11 to PXnm may include a pixel driving circuit and a displayelement.

Pixels PX11 to PXnm arranged in a matrix shape are illustrated as anexample in FIG. 2. However, the inventive concepts are not limitedthereto. In another embodiment, pixels PX11 to PXnm may be arranged in apentile shape.

FIG. 3 illustrates a central portion of display area DA. Display area DAmay include pixel areas PXA and peripheral area NPXA. Peripheral areaNPXA may surround each of pixel areas PXA and may correspond to aboundary area between pixel areas PXA. Pixel areas PXA may be arrangedin substantially the same shape as pixels PX11 to PXnm.

Pixel areas PXA may correspond to areas that substantially displaycolors. Pixel areas PXA may correspond to transmission areas in atransmission-type display panel or may correspond to light emittingareas in a light emitting display panel. Pixel areas PXA may beclassified into a plurality of groups on the basis of colors displayedby pixel areas PXA. In other words, each of pixel areas PXA may displayone of primary colors. The primary colors may include a red color, agreen color, a blue color, and a white color.

Gap GP is defined between first display substrate 100 and second displaysubstrate 200. Signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-Ddescribed with reference to FIG. 2 may be included in one of firstdisplay substrate 100 and second display substrate 200. Pixels PX11 toPXnm may be included in one of first display substrate 100 and seconddisplay substrate 200. Alternatively, some components of pixels PX11 toPXnm may be included in first display substrate 100, and othercomponents of pixel PX11 to PXnm may be included in second displaysubstrate 200. Pixels PX11 to PXnm may be disposed between the basesubstrate of first display substrate 100 and the base substrate ofsecond display substrate 200.

FIG. 4 illustrates a portion of non-display area NDA which may beconnected to gate driving unit GDC and data driving unit DDC. A portionin which second auxiliary signal lines PL-D are disposed is illustratedin FIG. 4.

Insulating structure IS that has a side surface substantially alignedwith the side surface of display panel DP may overlap second auxiliarysignal lines PL-D. Insulating structure IS may have a multi-layeredstructure. Insulating structure IS having a two-layer structure isillustrated as an example in FIG. 4. One of first insulating structureIS1 and second insulating structure IS2 of insulating structure IS maycorrespond to a portion of one of first display substrate 100 and seconddisplay substrate 200.

Even though a portion of insulating structure IS is illustrated in FIG.4, insulating structure IS may extend along an edge of display panel DPin a plan view and may have a closed loop shape in a plan view.

Sealing structure SS may further be disposed between first displaysubstrate 100 and second display substrate 200. Sealing structure SS maybe disposed inside insulating structure IS. In other words, sealingstructure SS may be closer to display area DA than insulating structureIS. That is, sealing structure SS may be disposed between insulatingstructure IS and display area DA. Sealing structure SS may surround gapGP. In other words, first display substrate 100, second displaysubstrate 200 and sealing structure SS may define a sealed space.

Sealing structure SS may have a structure different from that ofinsulating structure IS. Sealing structure SS may have a single-layeredstructure. Sealing structure SS may include a photocurable organicmaterial, a thermosetting organic material, or a glass frit sealant.

FIG. 5 is an equivalent circuit diagram of a pixel of a display panel ofthe display device of FIG. 2. FIGS. 6A to 6C are schematiccross-sectional views of display areas of display panels constructedaccording to some embodiments of the invention. FIG. 7 is a schematiccross-sectional view of a non-display area of a display panelconstructed according to an embodiment of the invention. FIG. 8 is across-sectional image of a non-display area of a display panelconstructed according to an embodiment of the invention.

FIGS. 5 to 8 illustrate liquid crystal display panels as an example ofdisplay panel DP. Pixel PXij connected to the i^(th) gate line GLi andthe j^(th) data line DLj is illustrated as an example in FIG. 5.

Pixel PXij may include thin film transistor TR (hereinafter, referred toas ‘transistor’), liquid crystal capacitor Clc, and storage capacitorCst. Liquid crystal capacitor Clc may correspond to a display element,and transistor TR and storage capacitor Cst may constitute a pixeldriving circuit. The numbers of transistor TR and storage capacitor Cstmay be changed depending on an operating mode of the liquid crystaldisplay panel.

Liquid crystal capacitor Clc may store a pixel voltage outputted fromtransistor TR. Arrangement of liquid crystal directors included inliquid crystal layer LCL may be changed depending on the amount ofcharge stored in liquid crystal capacitor Clc. In other words, theliquid crystal directors may be controlled by an electric field formedbetween two electrodes of liquid crystal capacitor Clc. Light incidentto liquid crystal layer LCL may be transmitted or blocked according tothe arrangement of the liquid crystal directors.

Storage capacitor Cst is connected in parallel to liquid crystalcapacitor Clc. Storage capacitor Cst maintains the arrangement of theliquid crystal directors for a certain period.

Transistor TR includes control electrode GE connected to the i^(th) gateline GLi, active part AL overlapping control electrode GE, inputelectrode SE connected to the j^(th) data line DLi, and output electrodeDE spaced apart from input electrode SE.

Liquid crystal capacitor Clc includes pixel electrode PE and commonelectrode CE. Storage capacitor Cst includes pixel electrode PE and aportion of storage line STL overlapping pixel electrode PE.

The i^(th) gate line GLi and storage line STL are disposed on onesurface of first base substrate BS1 of first display substrate 100.Control electrode GE is branched from the i^(th) gate line GLi. Thei^(th) gate line GLi and storage line STL may include a metal (e.g.,aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr),tantalum (Ta), or titanium (Ti)) or any alloy thereof. In an embodiment,the i^(th) gate line GLi and storage line STL may have a multi-layeredstructure (e.g., a titanium layer and a copper layer).

First base substrate BS1 may be a glass substrate or a plasticsubstrate. First insulating layer 10 may be disposed on one surface offirst base substrate BS1 and may cover control electrode GE and storageline STL. First insulating layer 10 may include at least one of aninorganic material and an organic material. For example, firstinsulating layer 10 may include a silicon nitride layer, a siliconoxynitride layer, a silicon oxide layer, a titanium oxide layer, and analuminum oxide layer. In an embodiment, first insulating layer 10 mayinclude a multi-layered structure (e.g., a silicon nitride layer and asilicon oxide layer).

Active part AL overlapping control electrode GE is disposed on firstinsulating layer 10. Active part AL may include semiconductor layer SCLand ohmic contact layer OCL. Semiconductor layer SCL is disposed onfirst insulating layer 10, and ohmic contact layer OCL is disposed onsemiconductor layer SCL.

Semiconductor layer SCL may include amorphous silicon or poly-silicon.Alternatively, semiconductor layer SCL may include a metal oxidesemiconductor. Ohmic contact layer OCL may be doped with dopants. Aconcentration of the dopants in ohmic contact layer OCL may be higherthan a concentration of dopants in semiconductor layer SCL. Ohmiccontact layer OCL may include two portions spaced apart from each other.In an embodiment of the invention, ohmic contact layer OCL may have aunitary body.

Output electrode DE and input electrode SE are disposed on active partAL. Output electrode DE and input electrode SE are spaced apart fromeach other. Each of output electrode DE and input electrode SE partiallyoverlaps control electrode GE.

Second insulating layer 20 is disposed on first insulating layer 10 andcovers active part AL, output electrode DE, and input electrode SE.Second insulating layer 20 may include at least one of an inorganicmaterial and an organic material. For example, second insulating layer20 may include a silicon nitride layer, a silicon oxynitride layer, asilicon oxide layer, a titanium oxide layer, and an aluminum oxidelayer. In an embodiment, second insulating layer 20 may include amulti-layered structure (e.g., a silicon nitride layer and a siliconoxide layer).

Transistor TR having a staggered structure is illustrated as an examplein FIG. 6A. However, the structure of transistor TR is not limitedthereto. In another embodiment, transistor TR may have a planarstructure.

Third insulating layer 30 is disposed on second insulating layer 20.Third insulating layer 30 may be a single organic layer providing a flatsurface. In the illustrated embodiment, third insulating layer 30 mayinclude a plurality of color filters. The color filter may completelycover at least pixel area PXA as illustrated in FIG. 3. The colorfilters of adjacent pixels may partially overlap each other inperipheral area NPXA.

Fourth insulating layer 40 is disposed on third insulating layer 30.Fourth insulating layer 40 may be an inorganic layer covering the colorfilters. For example, fourth insulating layer 40 may include a siliconnitride layer, a silicon oxynitride layer, a silicon oxide layer, atitanium oxide layer, and an aluminum oxide layer. In an embodiment,fourth insulating layer 40 may include a multi-layered structure (e.g.,a silicon nitride layer and a silicon oxide layer).

Pixel electrode PE is disposed on fourth insulating layer 40. Pixelelectrode PE is connected to output electrode DE through contact holeCH10 penetrating second, third and fourth insulating layers 20, 30 and40. An alignment layer covering pixel electrode PE may be disposed onfourth insulating layer 40.

Second base substrate BS2 of second display substrate 200 may be a glasssubstrate or a plastic substrate. Black matrix layer BM is disposed on abottom surface of second base substrate BS2. Black matrix layer BM mayhave a shape corresponding to peripheral area NPXA as illustrated inFIG. 3. In other words, openings corresponding to pixel areas PXA may bedefined in black matrix layer BM.

At least one insulating layer covering black matrix layer BM aredisposed on the bottom surface of second base substrate BS2. Fifthinsulating layer 50 providing a substantially flat surface isillustrated as an example of the insulating layer disposed on the bottomsurface of second base substrate BS2 in FIG. 6A. Fifth insulating layer50 may include an organic material.

Common electrode CE is disposed on the bottom surface of second basesubstrate BS2. A common voltage is applied to common electrode CE. Avalue of the common voltage is different from that of the pixel voltage.However, the cross-section of pixel PXij of FIG. 6A is illustrated as anexample of the invention. In another embodiment, first display substrate100 and the second display substrate 200 may be turned over.

In the illustrated embodiment, the liquid crystal display panel of avertical alignment (VA) mode is described as an example. However, theinventive concepts are not limited thereto. Embodiments of the inventionmay be applied to a liquid crystal display panel of an in-planeswitching (IPS) mode, a fringe-field switching (FFS) mode, aplane-to-line switching (PLS) mode, a super vertical alignment (SVA)mode, or a surface-stabilized vertical alignment (SS-VA) mode or othermodes known in the art.

The liquid crystal display panel of the in-plane switching (IPS) mode isillustrated in FIG. 6B, and the liquid crystal display panel of theplane-to-line switching (PLS) mode is illustrated in FIG. 6C. In theliquid crystal display panel of the in-plane switching (IPS) mode, pixelelectrode PE and common electrode CE may be disposed on substantiallythe same layer. Each of pixel electrode PE and common electrode CE mayinclude a plurality of branch portions. The branch portions of pixelelectrode PE and the branch portions of common electrode CE may bealternately arranged. Common electrode CE may be connected to a signalline (e.g., storage line STL) receiving the common voltage throughcontact hole CH20.

In the liquid crystal display panel of the plane-to-line switching (PLS)mode, pixel electrode PE and common electrode CE may be disposed onfourth insulating layer 40 with sixth insulating layer 45 interposedtherebetween. Pixel electrode PE may include a plurality of branchportions or may include a plurality of slits.

Spacer CS may be disposed between first display substrate 100 and seconddisplay substrate 200. Spacer CS maintains gap GP as illustrated in FIG.3. Spacer CS may include a photosensitive organic material. Spacer CSoverlaps peripheral area NPXA. Spacer CS may overlap transistor TR.

As illustrated in FIG. 7, side surface PL-DS of auxiliary signal linePL-D is substantially aligned with side surface BS1-S of first basesubstrate BS1. Side surface of insulating structure IS is substantiallyaligned with side surface BS1-S of first base substrate BS1. Insulatingstructure IS includes first insulating structure IS1 that is in contactwith insulating layer 50 of second display substrate 200. Firstinsulating structure IS1 is disposed between insulating layer 50 andfirst base substrate BS1. In a case that an alignment layer is disposedunder insulating layer 50, first insulating structure IS1 may be incontact with the alignment layer. The alignment layer may be defined asanother insulating layer.

First insulating structure IS1 may include substantially the samematerial as spacer CS illustrated in FIGS. 6A to 6C. When second worksubstrate 200-W to be describe later with FIGS. 9A to 9C ismanufactured, first insulating structure IS1 and spacer CS may be formedby substantially the same process.

Insulating structure IS includes second insulating structure IS2 thatcorresponds to a portion of first display substrate 100. A side surfaceof second insulating structure IS2 is substantially aligned with sidesurface BS1-S of first base substrate BS1. Second insulating structureIS2 may have a two-layer structure. First layer IS2-1 of secondinsulating structure IS2 may include an organic material. First layerIS2-1 may include substantially the same material as third insulatinglayer 30 as illustrated in FIG. 6A to 6C. First layer IS2-1 may includesubstantially the same material as the color filter. Second layer IS2-2of second insulating structure IS2 may include an inorganic material.Second layer IS2-2 may be a portion of fourth insulating layer 40. In anembodiment of the invention, second layer IS2-2 may be omitted.

Connection pad CP is disposed on the side surface of display panel DP.Connection pad CP may be provided in plurality, and connection pads CPmay be in contact with side surfaces PL-DS of auxiliary signal linesPL-D, respectively. Connection pad CP may be in contact with sidesurface BS1-S of first base substrate BS1, side surface PL-DS ofauxiliary signal line PL-D, and the side surface of insulating structureIS. In one embodiment of the invention, connection pad CP may be incontact with side surface BS1-S of first base substrate BS1, the sidesurface of insulating structure IS and the side surface of second basesubstrate BS2. Connection pad CP being in contact with side surfaceIS2-S of second insulating structure IS2 is illustrated as an example inFIG. 7. Connection pad CP may include metal paste. The metal pasteincludes a mixture of a metal and an insulating material. Connection padCP may include silver paste.

Connection pad CP may be electrically connected to pad DCB-P of circuitsubstrate DCB through an anisotropic conductive film (ACF). The size ofthe pads DCB-P of circuit board DCB and the size of the anisotropicconductive film (ACF) may be set to correspond to the size of connectionpad CP. The anisotropic conductive film (ACF) may be replaced withsolder paste, and connection pad CP may be connected directly to padDCB-P of circuit substrate DCB.

Sealing structure SS may be disposed inside insulating structure IS andmay be disposed between common electrode CE and fourth insulating layer40. In the event that the alignment layers are disposed, sealingstructure SS is disposed between the alignment layers. Black matrixlayer BM is also disposed in non-display area NDA.

FIG. 8 shows auxiliary signal line PL-D overlapping with insulatingstructure IS and connection pad CP connected to auxiliary signal linePL-D. Insulating structure IS may be disposed to remove a gap betweenfirst and second display substrates 100 and 200 near the side surface ofdisplay panel DP. Thus, it is possible to prevent an end portion ofauxiliary signal line PL-D from being damaged in manufacturing processesto be described later.

FIG. 9A is a schematic perspective view of a work panel used in anexemplary method of manufacturing a display panel according to anembodiment of the invention. FIG. 9B is a schematic cross-sectional viewof the work panel of FIG. 9A. FIG. 9C is a schematic cross-sectionalview of a preliminary display panel cut from the work panel of FIG. 9A.FIG. 9D is a cross-sectional image of a display panel as a comparativeexample.

As illustrated in FIG. 9A, substantially the same process may beperformed on cell areas DP-C defined in work panel WP to form displaypanel DP as illustrated in FIGS. 5 to 7 in each of cell areas DP-C. Inmore detail, first work substrate 100-W and second work substrate 200-Wmay be coupled to each other to form work panel WP. First work substrate100-W may have substantially the same structure as first displaysubstrate 100 described with reference to FIGS. 5 to 7 in each of cellareas DP-C, and second work substrate 200-W may have substantially thesame structure as second display substrate 200 described with referenceto FIGS. 5 to 7 in each of cell areas DP-C.

As illustrated in FIG. 9B, a structure extending from structures of cellareas DP-C may be disposed in boundary area BA of work panel WP. Workpanel WP may be cut along cutting line CL illustrated in FIG. 9B by, forexample, a scribing process, and thus preliminary display panel DP-P ofFIG. 9C may be separated.

A side surface of preliminary display panel DP-P of FIG. 9C is in anon-uniform state, as compared with the side surface of display panel DPof FIG. 7. The side surface of preliminary display panel DP-P is groundusing grinder GM, which is known as a grinding process. A side surfaceof insulating structure IS, a side surface of auxiliary signal linePL-D, a side surface of first base substrate BS1 and a side surface ofsecond base substrate BS2 may be substantially aligned with one anotherusing the grinding process. A cross-sectional shape of auxiliary signalline PL-D may be different depending on the grinding method (e.g., arotational direction of grinder GM). However, the side surface ofauxiliary signal line PL-D and the side surface of first base substrateBS1 may be substantially aligned with each other regardless of thegrinding method. The side surface of auxiliary signal line PL-D of FIG.8 is formed according to the rotational direction of grinder GM of FIG.9C.

As used herein, the term “substantially aligned” may include a case inwhich the side surfaces of insulating structure IS, auxiliary signalline PL-D and first and second base substrates BS1 and BS2 constituteone surface, and the term “substantial alignment” may also includevariations as a result of manufacturing techniques and/or processtolerances. For example, the side surface of auxiliary signal line PL-Dmay have a fine curved surface formed by grinder GM. A corner defining acurved side surface of auxiliary signal line PL-D may be aligned with acorner defining the side surface of insulating structure IS.

Damage/deformation of the end portion of auxiliary signal line PL-D maybe prevented in the grinding process. This may be because insulatingstructure IS supports first display substrate 100 and second displaysubstrate 200 to prevent the side surface of display panel DP from beingdamaged/deformed by friction of grinder GM.

FIG. 9D shows a cross-section of display panel DP-S as a comparativeexample. FIG. 9D shows a cross-section corresponding to that of FIG. 8.However, since insulating structure IS is not disposed in region GP-Ecorresponding to insulating structure IS in FIG. 9D, region GP-E isfilled with sludge generated in the grinding process. In addition, thesludge of first base substrate BS1 covers a side surface of auxiliarysignal line PL-D, and thus auxiliary signal line PL-D is not completelyconnected to connection pad CP. In other words, a contact resistancebetween auxiliary signal line PL-D and connection pad CP is increased.

FIG. 10 is a schematic cross-sectional view of a non-display area of adisplay panel constructed according to an embodiment of the invention.FIG. 10 illustrates a cross-sectional view corresponding to FIG. 7.Hereinafter, the descriptions to the same or substantially the samecomponents as in the embodiments of FIGS. 1 to 9D will be omitted toavoid redundancy.

Display panel DP according to the illustrated embodiment furtherincludes floating electrode FE, as compared with display panel DPdescribed with reference to FIGS. 1 to 8. Floating electrode FE overlapsauxiliary signal line PL-D and first layer IS2-1 of second insulatingstructure IS2. Floating electrode FE is disposed between auxiliarysignal line PL-D and first layer IS2-1 of second insulating structureIS2. Floating electrode FE may be disposed on substantially the samelayer as input electrode SE of the transistor.

A side surface of floating electrode FE may be substantially alignedwith the side surface of first base substrate BS1. Connection pad CP maybe in contact with the side surface of floating electrode FE.

Floating electrode FE is shown in FIG. 8. Floating electrode FE may bedisposed on auxiliary signal line PL-D to withstand stress applied toauxiliary signal line PL-D in the grinding process, and thusdamage/deformation of auxiliary signal line PL-D may be prevented.

FIG. 11 is an equivalent circuit diagram of a pixel that may be employedin any of the display panels constructed according to an embodiment ofthe invention. FIG. 12 is a schematic cross-sectional view of a displayarea of a display panel constructed according to an embodiment of theinvention. FIG. 13 is a schematic cross-sectional view of a non-displayarea of a display panel constructed according to an embodiment of theinvention.

The liquid crystal display panels were described as examples withreference to FIGS. 5 to 8. However, the principles of the invention mayalso be applied to other types of display, such as an organic lightemitting display panel as illustrated in FIGS. 11 to 13. Hereinafter,differences between the liquid crystal display panel and the organiclight emitting display panel will be mainly described to avoidredundancy.

As illustrated in FIG. 11, pixel PXij may include an organic lightemitting diode OLED and a pixel driving circuit. The organic lightemitting diode OLED may be a front surface type light emitting diode ora back surface type light emitting diode. The pixel driving circuit mayinclude first thin film transistor (or a switching transistor) TR1,second thin film transistor (or a driving transistor) TR2, and capacitorCst. First power source voltage ELVDD is provided to second thin filmtransistor TR2, and second power source voltage ELVSS is provided to theorganic light emitting diode OLED. Second power source voltage ELVSS maybe lower than first power source voltage ELVDD. However, the pixeldriving circuit may not be limited thereto but may be variouslymodified. The pixel driving circuit may further include a plurality oftransistors and/or may include two or more capacitors. In anotherembodiment, the organic light emitting diode OLED may be connectedbetween power line PL and second thin film transistor TR2.

As illustrated in FIG. 12, circuit element layer DP-CL, display elementlayer DP-OLED and thin film encapsulation layer TFE are sequentiallystacked on first base substrate BS1. In the illustrated embodiment,circuit element layer DP-CL may include buffer layer BFL correspondingto an inorganic layer, first insulating layer 10, second insulatinglayer 20, and third insulating layer 30. First insulating layer 10 andsecond insulating layer 20 may be inorganic layers, and third insulatinglayer 30 may be an organic layer. Materials of the inorganic layers andthe organic layer are not limited to specific materials, and bufferlayer BFL may be disposed or omitted in some embodiments of theinvention.

Semiconductor pattern OSP1 (hereinafter, referred to as ‘firstsemiconductor pattern’) of first thin film transistor TR1 andsemiconductor pattern OSP2 (hereinafter, referred to as ‘secondsemiconductor pattern’) of second thin film transistor TR2 are disposedon buffer layer BFL. Each of first and second semiconductor patternsOSP1 and OSP2 may be at least one material selected from the groupconsisting of amorphous silicon, poly-silicon, and a metal oxidesemiconductor.

First insulating layer 10 is disposed on first semiconductor patternOSP1 and second semiconductor pattern OSP2. Control electrode GE1(hereinafter, referred to as ‘first control electrode’) of first thinfilm transistor TR1 and control electrode GE2 (hereinafter, referred toas ‘second control electrode’) of second thin film transistor TR2 aredisposed on first insulating layer 10. First control electrode GE1 andsecond control electrode GE2 may be formed using substantially the samephotolithography process as scan lines GLi formed with reference to FIG.11.

Second insulating layer 20 is disposed on first insulating layer 10 andcovers first control electrode GE1 and second control electrode GE2.Input electrode DE1 (hereinafter, first input electrode) and outputelectrode SE1 (hereinafter, first output electrode) of first thin filmtransistor TR1 and input electrode DE2 (hereinafter, second inputelectrode) and output electrode SE2 (hereinafter, second outputelectrode) of second thin film transistor TR2 are disposed on secondinsulating layer 20.

First input electrode DE1 and first output electrode SE1 are connectedto portions of first semiconductor pattern OSP1 via first through-holeCH1 and second through-hole CH2 penetrating first and second insulatinglayers 10 and 20, respectively. Second input electrode DE2 and secondoutput electrode SE2 are connected to portions of second semiconductorpattern OSP2 via third through-hole CH3 and fourth through-hole CH4penetrating first and second insulating layers 10 and 20, respectively.Meanwhile, in other embodiments, at least one of first thin filmtransistor TR1 or second thin film transistor TR2 may have a bottom gatestructure.

Third insulating layer 30 is disposed on second insulating layer 20 andcovers first input electrode DE1, second input electrode DE2, firstoutput electrode SE1, and second output electrode SE2. Third insulatinglayer 30 may provide a flat surface.

Display element layer DP-OLED is disposed on third insulating layer 30.Display element layer DP-OLED may include pixel defining layer PDL andthe organic light emitting diode OLED. Pixel defining layer PDL mayinclude an organic material. First electrode AE is disposed on thirdinsulating layer 30. First electrode AE is connected to second outputelectrode SE2 via fifth through-hole CH5 penetrating third insulatinglayer 30. Opening OP is defined in pixel defining layer PDL. Opening OPof pixel defining layer PDL exposes at least a portion of firstelectrode AE. In an embodiment of the invention, pixel defining layerPDL may be omitted.

Display area DA may include pixel area (or a light emitting area) PXAand peripheral area (or a non-light emitting area) NPXA adjacent topixel area PXA. Peripheral area NPXA may surround pixel area PXA. In theillustrated embodiment, pixel area PXA is defined to correspond to apartial area of first electrode AE, which is exposed through opening OP.

In an embodiment of the invention, pixel area PXA may also overlap atleast one of first thin film transistor TR1 and second thin filmtransistor TR2. Opening OP may be more widened, and first electrode AEand light emitting layer EML to be described later may also be morewidened.

Hole control layer HCL may be disposed in common in pixel area PXA andperipheral area NPXA. Even though not shown in the drawings, a commonlayer such as hole control layer HCL may be formed in common in pixelareas PXA as illustrated in FIG. 3.

Light emitting layer EML is disposed on hole control layer HCL. Lightemitting layer EML may be disposed in an area corresponding to openingOP. In other words, light emitting layers EML of pixel areas PXA may beseparated from each other. Light emitting layer EML may include anorganic material and/or an inorganic material. Light emitting layer EMLmay generate light having a predetermined color.

In the illustrated embodiment, the patterned light emitting layer EML isillustrated as an example. However, in another embodiment, lightemitting layer EML may be disposed in common in pixel areas PXA asillustrated in FIG. 3. In this case, light emitting layer EML maygenerate white light. In addition, light emitting layer EML may have amulti-layered structure called ‘a tandem’.

Electron control layer ECL is disposed on light emitting layer EML. Eventhough not shown in the drawings, electron control layer ECL may beformed in common in pixel areas PXA as illustrated in FIG. 3. Secondelectrode CE is disposed on electron control layer ECL. Second electrodeCE is disposed in common in pixel areas PXA as illustrated in FIG. 3.

Thin film encapsulation layer TFE is disposed on second electrode CE.Thin film encapsulation layer TFE is disposed in common in pixel areasPXA as illustrated in FIG. 3. In the illustrated embodiment, thin filmencapsulation layer TFE directly covers second electrode CE. In anembodiment of the invention, a capping layer covering second electrodeCE may further be disposed between thin film encapsulation layer TFE andsecond electrode CE. In this case, thin film encapsulation layer TFE maydirectly cover the capping layer.

In an embodiment of the invention, the organic light emitting diode OLEDmay further include a resonance structure for controlling a resonancedistance of light generated from light emitting layer EML. The resonancestructure may be disposed between first electrode AE and secondelectrode CE, and a thickness of the resonance structure may bedetermined depending on a wavelength of the light generated from lightemitting layer EML.

Second base substrate BS2 is spaced apart from thin film encapsulationlayer TFE. Second base substrate BS2 may include a glass substrate or aplastic substrate. Second base substrate BS2 corresponds to seconddisplay substrate 200 in the illustrated embodiment. However, in anotherembodiment, various functional layers may be disposed on a top surfaceor a bottom surface of second base substrate BS2.

As illustrated in FIG. 13, thin film encapsulation layer TFE, electroncontrol layer ECL and hole control layer HCL extend into non-displayarea NDA. Insulating structure IS is disposed between second basesubstrate BS2 and first base substrate BS1. A side surface of insulatingstructure IS is substantially aligned with a side surface of first basesubstrate BS1. Insulating structure IS having a two-layer structure isillustrated as an example in the illustrated embodiment. However, theinventive concepts are not limited thereto.

First insulating structure IS1 and second insulating structure IS2 ofinsulating structure IS may be substantially the same as firstinsulating structure IS1 and second insulating structure IS2 describedwith reference to FIG. 7. However, the inventive concepts are notlimited thereto. In other embodiments, each of first and secondinsulating structures IS1 and IS2 may include an organic layer and maybe variously modified.

Insulating structure IS is disposed between the topmost surface of firstdisplay substrate 100 and the bottommost surface of second displaysubstrate 200. In the illustrated embodiment, the topmost surface offirst display substrate 100 corresponds to a top surface of thin filmencapsulation layer TFE, and the bottommost surface of second displaysubstrate 200 corresponds to a bottom surface of second base substrateBS2. However, the inventive concepts are not limited thereto. In anotherembodiment, thin film encapsulation layer TFE, electron control layerECL and hole control layer HCL may not be disposed in non-display areaNDA, and a top surface of pixel defining layer PDL may correspond to thetopmost surface of first display substrate 100.

According to the above descriptions, a connection pad may be disposed ona side surface of a display panel, and thus a circuit substrate may beconnected to the side surface of the display panel. Since a connectionarea of the circuit substrate and the display panel is defined on theside surface of the display panel, the non-display area may be reducedand the structural integrity may be increased.

Since a side surface of an insulating structure is substantially alignedwith the side surface of the display panel and a side surface of asignal line, it is possible to prevent the signal line from beingdamaged and/or deformed in a manufacturing process such as a grindingprocess. A contact area defined on the side surface of the signal linemay be secured, thereby reducing a contact resistance between thecircuit substrate and the display panel.

Although certain embodiments and implementations have been describedherein, other embodiments and modifications will be apparent from thisdescription. Accordingly, the inventive concepts are not limited to suchembodiments, but rather to the broader scope of the appended claims andvarious obvious modifications and equivalent arrangements as would beapparent to a person of ordinary skill in the art.

What is claimed is:
 1. A display panel comprising: a first substratehaving a top surface and a side surface, the top surface including adisplay area and a non-display area outside the display area; a secondsubstrate facing the first substrate; a first insulating structuredisposed between the second substrate and the first substrate, whereinthe first insulating structure overlaps the non-display area withoutoverlapping the display area; an organic light emitting diode betweenthe first substrate and the second substrate and overlapping the displayarea; a thin film encapsulation layer on the organic light emittingdiode; a signal line having a side surface substantially aligned withthe side surface of the first substrate, wherein the signal line isdisposed on the first substrate; a second insulating structureoverlapping the signal line and disposed between the first substrate andthe first insulating structure, wherein the second insulating structurehas a side surface substantially aligned with the side surface of thefirst substrate; and a connection pad being in contact with the sidesurface of the signal line, wherein the second insulating structureincludes an organic layer overlapping the signal line and thenon-display area without overlapping the display area, and wherein thefirst insulating structure and the second insulating structure aredisposed on the thin film encapsulation layer.
 2. The display panel ofclaim 1, wherein the second substrate is spaced apart from the thin filmencapsulation layer.
 3. A display panel comprising: a first substratehaving a top surface and a side surface, the top surface including adisplay area and a non-display area outside the display area; a secondsubstrate facing the first substrate; a first insulating structuredisposed between the second substrate and the first substrate, whereinthe first insulating structure overlaps the non-display area withoutoverlapping the display area; an organic light emitting diode betweenthe first substrate and the second substrate and overlapping the displayarea; a thin film encapsulation layer on the organic light emittingdiode; a signal line having a side surface substantially aligned withthe side surface of the first substrate, wherein the signal line isdisposed on the first substrate; a pixel defining layer on the firstsubstrate; a second insulating structure overlapping the signal line anddisposed between the first substrate and the first insulating structure,wherein the second insulating structure has a side surface substantiallyaligned with the side surface of the first substrate; and a connectionpad being in contact with the side surface of the signal line, whereinthe second insulating structure includes an organic layer overlappingthe signal line and the non-display area without overlapping the displayarea, and wherein the first insulating structure and the secondinsulating structure are disposed on the pixel defining layer.
 4. Thedisplay panel of claim 1, further comprising a thin film transistorelectrically connected to the organic light emitting diode, and whereinthe signal line is disposed on substantially the same layer as a controlelectrode of the thin film transistor.
 5. The display panel of claim 1,further comprising a seal disposed between the first substrate and thesecond substrate and spaced apart from the organic layer of the secondinsulating structure.
 6. A display panel comprising: a first substratehaving a top surface and a side surface, the top surface including adisplay area and a non-display area outside the display area; a secondsubstrate facing the first substrate; a first insulating structuredisposed between the second substrate and the first substrate, whereinthe first insulating structure overlaps the non-display area withoutoverlapping the display area; an organic light emitting diode betweenthe first substrate and the second substrate and overlapping the displayarea; a thin film encapsulation layer on the organic light emittingdiode; a signal line having a side surface substantially aligned withthe side surface of the first substrate, wherein the signal line isdisposed on the first substrate; a second insulating structureoverlapping the signal line and disposed between the first substrate andthe first insulating structure, wherein the second insulating structurehas a side surface substantially aligned with the side surface of thefirst substrate; a floating electrode overlapping the signal line andthe second insulating structure, and a connection pad being in contactwith the side surface of the signal line, wherein the second insulatingstructure includes an organic layer overlapping the signal line and thenon-display area without overlapping the display area, and wherein thefloating electrode is disposed between the signal line and the organiclayer of the second insulating structure.
 7. The display panel of claim6, wherein the floating electrode contacts the connection pad.
 8. Thedisplay panel of claim 6, further comprising a thin film transistorelectrically connected to the organic light emitting diode, and whereinthe floating electrode is disposed on substantially the same layer as aninput electrode or an output electrode of the thin film transistor. 9.The display panel of claim 1, further comprising a circuit substrateelectrically connected to the connection pad.
 10. The display panel ofclaim 1, wherein the signal line comprises copper, and the connectionpad comprises silver paste.
 11. The display panel of claim 1, whereinthe second insulating structure contacts the first insulating structure.12. The display panel of claim 1, wherein the connection pad contactsthe side surface of the first substrate and the side surface of thesecond insulating structure.